An integrated memory for instance in the form of a DRAM (Dynamic Random Access Memory) generally has a memory cell array, which comprises word lines and bit lines. The memory cells, in each case, are arranged at crossover points of the word lines and bit lines. The memory cells usually used in integrated dynamic random access memories have a storage capacitance and a selection transistor. The storage capacitances of the memory cells are, in each case, connected via the selection transistor to one of the bit lines by which a data signal is read out or written in. The control input of the selection transistor is connected to one of the word lines. A word line selects selection transistors from corresponding memory cells along the word line. The selection transistors are opened. If the respective selection transistor is open, then the charge stored in the cell capacitance can pass onto the corresponding bit line and from there into a read-write amplifier.
During a memory access, a word line is activated. As a result, the memory cells arranged along a word line are, in each case, conductively connected to a bit line via the respective selection transistor. In this case, the stored charge is divided up in accordance with the memory cell capacitance and bit line capacitance. In accordance with the ratio of these two capacitances (i.e., transfer ratio), this leads to a deflection of the bit line voltage. The sense amplifier situated at one end of the bit line compares this voltage with the constant voltage on the associated complementary bit line and amplifies the relatively small potential difference between the bit line and the complementary bit line until the bit line has reached the full signal level for a stored logic 1, which, for example, corresponds to a positive supply potential, or the signal level for a logic 0, which, for example, corresponds to a reference potential. The inverse signal levels are reached at the same time on the associated complementary bit line. Since the relevant selection transistor remains open during this operation, the signal is simultaneously written back to the memory cell again (i.e., a refresh). As a result, any losses of the stored charge caused by leakage can be compensated for again. Therefore, during the memory access described not only is the memory cell capacitance charged, but it is necessary for the entire capacitance of the corresponding bit lines to be subjected to charge reversal.
In order to achieve a compact arrangement of the memory cell array, the longest possible bit lines are sought. However, this leads to correspondingly high bit line capacitances. The consequence is a reduction of the memory cell signal to be detected by the sense amplifier as a result of impairment of the transfer ratio and an increased coupling between adjacent bit lines with disturbing crosstalk.